1. Field of the Invention
The present invention relates to a charge coupled device (CCD) and, more particularly, to a CCD and method of fabricating the same, which reads signal charges completely and increases the fill factor of its pixel, to improve the sensitivity.
2. Discussion of Related Art
A conventional CCD is constructed in such a manner that photodiodes are arranged in matrix form, and vertical charge coupled devices (VCCDs) receiving charges accumulated in the photodiodes and transmitting them to horizontal charge coupled devices (HCCDs) are formed in a row between the photodiodes. At present, a 4-phase VCCD using triple polysilicon layers is employed to the vertical charge transfer region of quarter-inch three hundreds thirty thousands pixels of progressive scan CCD (PS-CCD). A conventional CCD having the 4-phase VCCD structure using the triple polysilicon layers and method of fabricating the same are explained below with reference to the attached drawings. FIG. 1 is a plan view of the conventional 4-phase CCD using the triple polysilicon layers, FIG. 2A is a cross-sectional view of the conventional CCD, taken along line Ixe2x80x94I of FIG. 1, FIG. 2B is a cross-sectional view of the conventional CCD, taken along line IIxe2x80x94II of FIG. 1, and FIG. 2C is a cross-sectional view of the conventional CCD, taken along line IIIxe2x80x94III of FIG. 1. FIG. 3 show readout clocks of the conventional CCD, and FIGS. 4A to 4D are cross-sectional views showing a method of fabricating the conventional CCD.
The prior art realized by the aforementioned conventional CCD is about transfer gates constructing the VCCD, which transmit charges accumulated in the photodiodes to the HCCD. Referring to FIGS. 1, 2A, 2B and 2C, the conventional CCD is constructed in such a manner that a P-well 2 is formed in an N-type semiconductor substrate 1 to a predetermined depth, and a buried charge coupled device (BCCD) 3 is formed in P-well 2 in the direction of VCCD. First transfer gates 7 formed of a first polysilicon layer are formed in parallel on BCCD 3 and between photodiodes 4 in the row direction, having a specific interval. Second and third transfer gates 10a and 10b are superposed on both edges of first transfer gate 7 in the region between photodiodes 4 in the row direction and a region where the VCCD is formed, and also arranged on edges of photodiodes 4 in parallel. A fourth transfer gate 13a is formed on first transfer gate 7 between photodiodes 4, and partially superposed on second transfer gate 10a, third transfer gate 10b, BCCD 3 and neighboring another second transfer gate 10c in the VCCD region.
A method of fabricating first, second, third and fourth transfer gates 7, 10a, 10b and 13a formed between photodiodes 4 arranged in the row direction is described below. Referring to FIG. 4A, P-type ions are implanted into N-type semiconductor substrate 1 and thermal diffusion is carried out, to form P-well 2 in semiconductor substrate 1 to a predetermined depth. A pattern for forming photodiode 4 is formed on P-well 2, and N-type impurity ions are implanted into P-well 2 to a predetermined depth, to form a plurality of photodiodes 4 in matrix form. Then, a P-type channel stop region 5 is formed in a portion of P-well 2, placed between photodiodes 4, so as to come into contact with one side of each of photodiodes 4 adjacent to each other in the row direction. A first interlevel oxide layer 6 is formed on the overall surface of the substrate thinly, and a first polysilicon layer is formed thereon. First polysilicon layer is anisotropic-etched, to be left on channel stop region 5 placed between photodiodes 4 arranged in the row direction and on the VCCD region, forming first transfer gate 7.
Referring to FIG. 4B, an oxide layer is deposited through chemical vapor deposition (CVD) and anisotropic-etched, to be left on the center of first transfer gate 7, forming a block oxide layer 8. A second interlevel oxide layer 9 and second polysilicon layer 10 are formed on first transfer gate 7. A photoresist 11 is coated on second polysilicon layer 10, and then selectively exposed and developed, to be patterned. Referring to FIG. 4C, second polysilicon layer 10 is anisotropic-etched using the patterned photoresist 11 as a mask, to form second and third transfer gates 10a and 10b which are superposed on both edges of first transfer gate 7 respectively and arranged on neighboring photodiodes 4 in parallel. A third interlevel oxide layer 12 is formed on second and third transfer gates 10a and 10b, and a third polysilicon layer 13 is formed thereon. A photoresist 14 is coated on third polysilicon layer 13, and patterned through exposure and development processes.
Referring to FIG. 4D, third polysilicon layer 13 and third interlevel oxide layer 12 are anisotropic-etched using the patterned photoresist as a mask, to form fourth transfer gate 13a which is placed on first transfer gate 7 between photodiodes 4 arranged in the row direction and superposed on first transfer gate 7, second transfer gate 10a and another transfer gate 10c of neighboring photodiode 4 in the VCCD region. The operation of the above conventional CCD is explained below. As shown in FIG. 3, fourth transfer gate 13a formed of third polysilicon layer 13, formed between photodiodes 4 in the row direction, is clocked, that is, single readout is carried out to fourth transfer gate 13a, when the charges accumulated in the photodiode are transferred to the VCCD, to thereby read-out the charges to the VCCD. Then, the charges, which have been moved to the VCCD, are transmitted to the HCCD according to clock timings TG1, TG2, TG3 and TG4 of first, second, third and fourth transfer gates. Here, it is difficult to transmit the charges stored in one photodiode 4 to the VCCD completely because second and third transfer gates 10a and 10b come into contact with neighboring photodiodes 4. Thus, only fourth transfer gate 13a is clocked when the charges are transmitted from photodiode 4 to the VCCD.
However, the aforementioned conventional CCD has the following problems. First of all, since the second and third transfer gates placed between the photodiodes in the row direction are superposed on one side of the first transfer gate, simultaneously, formed on the photodiode of the P-well, the capacitance between the polysilicon layers increases and their widths widen. Thus, the CCD is difficult to become smaller. Furthermore, only the fourth transfer gate formed of the third polysilicon layer is tri-level clocked when the signal charges are read-out. Accordingly, three-dimensional effect increases as the pixel size is reduced, obstructing complete readout.
Accordingly, the present invention is directed to a CCD and method of fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a CCD and method of fabricating the same, in which the fill factor of its pixel increases to improve the sensitivity, and signal charges are easily completely read-out at a low electrode voltage.
To accomplish the object of the present invention, there is provided a CCD having photodiodes in matrix form includes; a first interlevel insulating layer and first transfer gate sequentially formed between the photodiodes arranged in the row direction; a block insulating layer formed along the center of the first transfer gate; a second interlevel insulating layer formed on the first transfer gate; second and third transfer gates formed on the first transfer gate, being isolated from each other on the block insulating layer; a third interlevel insulating layer formed on the second and third transfer gates; and a fourth transfer gate formed on the third interlevel insulating layer, being placed on the second and third transfer gates.
A method of fabricating the CCD according to the present invention includes the steps of: forming a first interlevel insulating layer and first transfer gate between the photodiodes arranged in the row direction; forming a block insulating layer on the center of the first transfer gate; forming a second interlevel insulating layer on the first transfer gate; forming second and third transfer gates, to be superposed on the sides of the block insulating layer, isolated from each other on the block insulating layer and placed on the first transfer gate; forming a third interlevel insulating layer on the second and third transfer gates; and forming a fourth transfer gate on the second and third transfer gates.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.